In a typical first-in-first-out ("FIFO") memory, a write index and a read index are used to determine whether the FIFO is empty or full. The write and read indices may be maintained by a counter. If a synchronous binary counter is used to maintain the write and read indices, then two or more digital logic bits of the synchronous binary counter may simultaneously change at a particular time in response to a clock signal, resulting in undesirable transition noise and complex timing conditions. If a single transition counter is used to maintain the write and read indices, then only one digital logic bit of the counter changes in response to a particular clock signal.
In order to maintain either the write or read indices, a synchronous binary counter or a single transition counter is reset to initially begin counting at an initial value. Typically, the counter's value is repeatedly incremented in response to positive-edge transitions of a clock signal, until the counter reaches its maximum value. When the counter reaches its maximum value, the next positive-edge transition of the clock signal results in the counter being automatically reset to its initial value. By design, the number of clock signals necessary for a typical counter to cycle from its initial value through to its maximum value and then back to its initial value is a power of two (2.sup.n, where n is the number of digital logic bits or output signals of the counter). For a typical binary counter, a variable count may be achieved, such that the number of clock signals necessary for the counter to cycle from its initial value through to its maximum value and then back to its initial value is not a power of two. To achieve such a variable count in a binary counter, a decoder detects when the counter reaches a specified maximum count, and the decoder thereupon resets the binary counter to its initial value. However, it is undesirable to apply the same approach to a single transition counter in order to achieve such a variable count, because more than one output signal of the single transition counter may change when the decoder resets the single transition counter to its initial value. In a FIFO, a variable count is desirable for the write and read indices, so that the number of storage locations in the FIFO is not required to be a power of two.
Consequently, a need has arisen for a method and circuitry for variable single transition counting in which only one digital logic bit of a variable single transition count changes in response to a clock signal.